How to disable most synthesis-optimizations options?

Looking at the schematic in your design, I see the following :

For the Butterfly_Zellen Schematic

1. Clock pins are tied to GND
2. PRE and CLR are tied together to VCC for both DFF blocks
3. PRE and CLR are tied together and given as Input to both DFFs.

What are you trying to achieve by doing this? If the CLK pins are tied to GND or VCC the DFF will not work and will be always OFF. Plus, since the PRE and CLR are tied together and have opposite functions, when you set this to VCC or GND, one DFF will be cleared while the other one will be Preset.

Please check your connections. If the connections are incorrect, the tool will analyze the circuit and if it determines that any of the inputs/outputs are stuck at '0' or '1' it will remove / optimize away the logic.