How to design divider circuit data path unit in Quartus II?

Hi,
the answer really depends on your exercise problem specification. If you are required to make a schematic (basically a structural design) comprised of elementary logic elements only, then have to build it from the scratch. The HDL code or a flow diagram of non-restoring algorithm can be used as a template.

A relative compact Verilog implementation copied from Stratix Cookbook is appended below. Question is which elementary logic/arithmetic functions are taken as granted and which have to be designed by yourself?

Regards
Frank