Altera_ForumHonored Contributor12 years agoHow to define clock while using flip flop I am new to VHDL and i am facing one problem while writing a code. In my circuit i have different components like half adder, and gate and flip flop. When i perform the check syntax, i receive an err...Show MoreNew Text Document.txt3 KB
Altera_ForumHonored Contributor12 years agoThe clue is in the error. In the "top" entity, you havent defined a clock signal or port.
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