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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:48:59 04/27/2013 
-- Design Name: 
-- Module Name:    project - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity andd is
		port ( in1, in2 : in  std_logic;
				 out1		 : out std_logic);		 
end andd;

architecture andd of andd is
begin
		out1 <= in1 and in2;
end andd;
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half_adder is 
		port ( X, Y   : in  std_logic;
				 Sum,C  : out std_logic);
end half_adder;

architecture half_adder of half_adder is
begin 
		Sum <= X xor Y;
		C   <= X and Y;
		
end half_adder;
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_FF is 
		port (Din,Clock : in  std_logic;
				Qout	  : out std_logic);
end D_FF;

architecture D_FF of D_FF is
begin
			process(Clock)
			begin
			if(Clock='1' and Clock'event) then 
			Qout <= Din;
			end if;
			end process;
end D_FF;
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
		port (A: in STD_LOGIC_VECTOR (1 downto 0);
				B: in STD_LOGIC_VECTOR (1 downto 0);
				Y: out STD_LOGIC_VECTOR (3 downto 0));
end top;

architecture top of top is

component andd port ( in1, in2 : in  std_logic;
				 out1		 : out std_logic);
end component;

component half_adder	port ( X, Y   : in  std_logic;
				 Sum,C  : out std_logic);
end component;

component D_FF	 port (Din,Clock : in  std_logic;
				Qout	  : out std_logic);
end component;

signal temp: STD_LOGIC_VECTOR (8 downto 1);

begin

a1: andd port map (A(0),B(0),temp(1));
a2: andd port map (A(1),B(0),temp(2));
a3: andd port map (A(0),B(1),temp(3));
a4: andd port map (A(1),B(1),temp(4));

ha1: half_adder port map (temp(3),temp(2),temp(5),temp(6));
ha2: half_adder port map (temp(4),temp(6),temp(7),temp(8));

ff1: D_FF port map (temp(1),Clock,Y(0));
ff2: D_FF port map (temp(5),Clock,Y(1));
ff3: D_FF port map (temp(7),Clock,Y(2));
ff4: D_FF port map (temp(8),Clock,Y(3));

end top;