How to deal with integrated clock gating cell on FPGA?

Hello NuvKFC,

if you are talking of hundreds for sure the FPGA (whichever you chose from any vendor) will not have enough dedicated clock lines for all of them. I encourage you to look at the specific device family user guide.

For the ones with higher fanout, use dedicated lines hfor that I suggest to use the ALTCLKCTRL IP to have the exact control you want.

The choice of regional or global depending on how much the logic could be spread through the device - i.e. even if the number of fanout is not very big sometimes there are other considerations to be made in case most of that is BLOCK Memory or DSP.

Note that in the chip planner you can always show the clock regions to get a better understanding on that. You can also force the placement of the logic in a specific part of the device creating a logic lock region.

For the remaining you could just change the coding to implement the clock enable synchronously with the data.

As all registers have the enable this will be converted by the tool appropriately to it.

However as pointed out by the documentation this is not reducing the power of the clock line as the clock line is always toggling (the enable is implemented at LAB or FF level depending on the family).

If your aim was to use clock gating to reduce power, for the clocks with higher fanout you shall use the ALT_CLKCTRL IP.

The enable implemented there (in most of the family) tied off the clock network itself, so you will get the most from power saving.

Lastly I want to point out that doing what I was suggesting require that you already have a good understanding of your design.
If this is not the case you can just try to synthetize your logic and Quartus by default shall recognize clock and promote them automatically, but sometimes you want to have better control and I assume this was your case.

Best regards