Contributor
New ContributorYou should just use the ALTCLKCTRL IP.
(user guide here: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/ug/ug-altclock.pdf)
This allow you to instantiate clock buffers, selecting the kind of clock routing you want to use (Global, Regional, etc) and you can instantiate into that the CLK_ENABLE through which you can gate the clock itself.
Please note that this is not the case with all device families (i.e. S10 and Agilex are a bit different from previous devices).
Have a look at the specific device family user guide for more info.
I also see that you are looking very old documentation (15.1.. today we are in 21.1 STD or 22.2 PRO), ensure to look the one specific for the Quartus version you are targeting.
i.e. for Quartus PRIME PRO you can have a look here:
https://www.intel.com/content/www/us/en/docs/programmable/683082/22-2/use-gated-clocks.html
(The easiest way to find Quartus Handbook is to go to this link:
https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html )
In terms of timing if you add a clock buffer of course you will have an inherent delay due to the buffer delay itself plus the routing you need to bring your clock signal to the buffer itself. However then all FF fed by this clock shall have the same delay (so almost neglectable skew).
You mention that in the design you are taking from ASIC, you have a lot of clocks signals (with I assume different gating).If this is the case consider to use non dedicated clock routing resource for clocks with low fanout.
In that case you can just AND the clock with an enable signal to gate it - anyway you will not incur in any timing penalties as the local routing is connecting ALMs (of course you will add to the clock a delay due to the signal passing through an ALM that without the clock gating you will not need).
For a design like this I suggest to turn off automatic clock global promotion in the tool and just add the ALTCLKCTRL IP for the clock you want to promote to global/regional/etc.
ContributorHi Marco_Intel
Thank you, Marco_Intel, very, very, much.
Yes, there are more than hundreds integrated clock gating cell (ICG) in the ASIC design.
I will try to replace all ICG with ALTCLKCTRL IP.
But I'm not sure whether all clock resource (Global, Regional, etc.) are enough or not.
And as you mention, there may can use non dedicated clock routing resource for clocks with low fanout.
How to do that?
Should I change all ICG to ALTCLKCTRL IP?
Or, change the coding style as following example?
Ex.
ICG:
always @(*)
if (~clk)
clk_en=en;
assign clock_gating=clk & clk_en;
|
|
|
ˇ
Change a ICG to a AND gate, and then use "Auto gated clock convert to clock enable" feature:
assign clock_gating=clk & clk_en;
Thank you very much.
