Honored ContributorHi,
I'm a Newbie to Quartus II. I have built a Decoder logic having 16 bit input and 20 bit output. I have created a Symbol file out of this. The problem is the 16 bit inputs are discrete. I need it in a Group so that I can interface with a 16 bit bus in another schematic.. Please guide me to make this possible.. Thanks and Regards Deena
Honored Contributor1. In simulation waveform
2. Select all inputs / outputs 3. Right click to select CREATE GROUP 4. Enter group name, for example, IN_BUS[19..0]Honored ContributorI'm sorry.. But that didn't update the Symbol created out of it.. I want the Symbol's input to be Vectorized
Honored ContributorWhat's the source file for your decoder? (HDL or schematic?)
If it's HDL then in verilog you would declare your input to be something like this "input [15:0] my_input_data;", and in VHDL it's something similar using a logic_vector (my VHDL is rusty so I'll leave that up to you to figure out). When you run the symbol generator on that you should end up bit a vectored input in the symbol. If you are using a schematic as the source then what I recommend doing is labeling a bus line to group all the individual signals together, then connect that bus line to a pin. It's probably easiest to label the input pin as "my_input_data[15:0]" in your schematic and then to use the individual bits you would draw individual bit lines that are labelled "my_input_data[0]", "my_input_data[1]", etc... in your logic. Quartus knows that when you use the subscripts with the same net name that they should be logically connected.
