How to Create Grouped (vectorized) inputs for a Symbol file created out of Schematic

What's the source file for your decoder? (HDL or schematic?)

If it's HDL then in verilog you would declare your input to be something like this "input [15:0] my_input_data;", and in VHDL it's something similar using a logic_vector (my VHDL is rusty so I'll leave that up to you to figure out). When you run the symbol generator on that you should end up bit a vectored input in the symbol.

If you are using a schematic as the source then what I recommend doing is labeling a bus line to group all the individual signals together, then connect that bus line to a pin. It's probably easiest to label the input pin as "my_input_data[15:0]" in your schematic and then to use the individual bits you would draw individual bit lines that are labelled "my_input_data[0]", "my_input_data[1]", etc... in your logic. Quartus knows that when you use the subscripts with the same net name that they should be logically connected.