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NWein's avatar
NWein
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

How to create a clock in SDC file for EMIF User Clock output?

I'm using an EMIF in a Cyclone 10GX design. I use the User Clock output for a lot of stuff, and need to define assorted timing constraints against it. Therefore I need it to be a named clock in my SDC file. I am unable to figure out a good way to do this.

I have derive_pll_clocks in there, but that doesn't help me with a name that I can use in other constraints.

My best idea was to compile, then go into the report and look at the list of clocks. And I find this:

  • ehive_single_top|ehive_dual_pd|emif0|emif_c10_0_core_usr_clk

However, if in my SDC file I try to use [get_clocks {*usr_clk}] in a constraint it says it's not found. I can't figure out why. There are no other clocks in the design whose names end in usr_clk.

Is there any sane way to do this? I feel like I must be missing something obvious.

4 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Is the timing analyzer showing this as an unconstrained clock? It should be constrained by the .sdc generated by the IP. Do you see it in the clocks report in the timing analyzer (not sure if what you mentioned was the timing analyzer report or something else)?

    If it's there and the unconstrained paths report does not show it as unconstrained, it should be able to be referenced in your other constraints. Have you tried searching for the clock using the Name Finder or the Report Timing dialog box in the GUI?

    #iwork4intel

  • NWein's avatar
    NWein
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    It was not unconstrained. I will try it in the name finder but it make take me a day to get back to it because I found a workaround in the meantime and it'll take me a bit of effort to go back and recreate it.

    What I did was to go look up the clocks in Timequest, and use the given source and target to create a new generated clock in my SDC file. That worked well enough for me to move forward, but doesn't seem like it should be the correct way to do it.

    I'll get back to you with your answers.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Since it's a clock generated by the IP, you shouldn't have to manually constrain it with a separate generated clock constraint, especially since the direct source is some internal clock of the IP.

    Check to make sure that the .qip file for the IP has been added to your Quartus project or that the IP's .sdc files are listed in the project files or timing analyzer settings. Perhaps the IP constraints were not added to your project somehow.

    #iwork4intel

  • NurAida_A_Intel's avatar
    NurAida_A_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi Sir,

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.