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harnhua's avatar
harnhua
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3 years ago

How to count levels of logic in timing paths?

Hi,

I am having some trouble finding out where the levels of logic are in my critical paths on a Stratix10 design in Quartus Prime 21.4 Pro Edition.

For example, in Timequest, the Statistics show 1 level of logic for a particular path.

However, the datapath itself seems to contain many more levels of logic:

In the table, rows 3 to 18 contain elements of type "IC" or "CELL" and "Combinational cell".

- Counting "CELL" types: 12 logic levels?

- Counting "CELL" types in different XY locations: 4 logic levels?

However much I tried, I could not figure out how to arrive at 1 level of logic.

Unfortunately I was not able to use the schematic view as this path is in an encrypted node.

Is there a document that explains how the number of logic levels are calculated?

What is the way to count them from the STA report?

Thanks!

15 Replies

  • harnhua's avatar
    harnhua
    Icon for New Contributor rankNew Contributor

    Hi,

    My apologies for the delay in responding. I have been requesting information from the customer.

    If I understand @Ryan_S_Intel 's comments correctly, levels of logic are not terribly useful beyond getting a rough sense of whether they are feasible given a path's timing budget - if not, some redesign is recommended. As you stated, maybe in reality there are too many things going on at the same time. Levels of logic is a single check and probably not the most important one.

    Regarding @Ryan_S_Intel 's question about Hyper-Timing, here is the Extra Info portion from a similar path (the design has since changed):

    Is it correct to say that Hyper-Timing is expected to move all endpoints away from ALM registers to hyper-register locations by default, if there are no restrictions?

    There does not seem to be any Retiming restrictions stated, yet the endpoints are still ALM Registers.

    Thank you for your comments. Much appreciated.

  • It's actually very common for registers with no retiming restrictions to still end up in the ALM register as the best possible location. We used to not have this extra_info report that showed retiming restrictions, and I would waste a lot of time trying to figure out if there was a restriction or not. With the report you can see the "--" and know you don't have to worry about retiming restrictions on the end points, and can then move on to more traditional optimizations, like reducing levels of logic. : ) (Note I'm not against analyzing levels of logic, but I'm not that interested in the absolute number.)

    Actually, since this is the worst path, you could look at the Retiming Critical Chain Report, to see how big the chain is and if there is any way you can pipeline or remove restrictions elsewhere in the Critical Chain.

    Your path is placed and routed well, has a carry-chain for half the logic which is very fast. I see your target is 2ns/500MHz, which is quite fast and usually takes very careful designing to close timing(though you are very close already, so are doing a good job, though squeezing out that last bit may be difficult) Good luck!

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor

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