How to count levels of logic in timing paths?

It's actually very common for registers with no retiming restrictions to still end up in the ALM register as the best possible location. We used to not have this extra_info report that showed retiming restrictions, and I would waste a lot of time trying to figure out if there was a restriction or not. With the report you can see the "--" and know you don't have to worry about retiming restrictions on the end points, and can then move on to more traditional optimizations, like reducing levels of logic. : ) (Note I'm not against analyzing levels of logic, but I'm not that interested in the absolute number.)

Actually, since this is the worst path, you could look at the Retiming Critical Chain Report, to see how big the chain is and if there is any way you can pipeline or remove restrictions elsewhere in the Critical Chain.

Your path is placed and routed well, has a carry-chain for half the logic which is very fast. I see your target is 2ns/500MHz, which is quite fast and usually takes very careful designing to close timing(though you are very close already, so are doing a good job, though squeezing out that last bit may be difficult) Good luck!