Ryan_S_Intel
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Re: How to count levels of logic in timing paths?
It's actually very common for registers with no retiming restrictions to still end up in the ALM register as the best possible location. We used to not have this extra_info report that showed retiming restrictions, and I would waste a lot of time trying to figure out if there was a restriction or not. With the report you can see the "--" and know you don't have to worry about retiming restrictions on the end points, and can then move on to more traditional optimizations, like reducing levels of logic. : ) (Note I'm not against analyzing levels of logic, but I'm not that interested in the absolute number.) Actually, since this is the worst path, you could look at the Retiming Critical Chain Report, to see how big the chain is and if there is any way you can pipeline or remove restrictions elsewhere in the Critical Chain. Your path is placed and routed well, has a carry-chain for half the logic which is very fast. I see your target is 2ns/500MHz, which is quite fast and usually takes very careful designing to close timing(though you are very close already, so are doing a good job, though squeezing out that last bit may be difficult) Good luck!3.2KViews0likes0CommentsRe: Quartus Fitter Crashing
This is not a response to the specific IE, but the ways you are seeing them move around. Note that Quartus is deterministic, e.g. if you start with the same project on the same machine(and let's delete the /db), it will do the exact same steps and give the same results. (If you change anything though, even as little as the name of a signal in your design, or maybe add a comment, then all bets are off). So internal errors should not jump around. When I've seen them, the user can repeat it and get the same one time-after-time. One thing I have seen when they jump around is corrupted memory on a machine. I hate suggesting that but throwing it out there. One other thing I've heard might have an effect is the Number of Processors used. Maybe try setting this to 1 (I think it defaults to max available) and see if it becomes consistent.4.4KViews0likes0CommentsRe: Constraints for ADC data input
I think you may want this: create_clock -name {RX_CLKp} -period 9.563 -waveform { 0.000 4.781 } {RX_CLKp} create_clock -name {RX_ADC_CLK} -period 9.563 -waveform {4.781 9.563} set_input_delay -clock RX_ADC_CLK -max 0.0 [get_ports {RX_D[*]}] set_input_delay -clock RX__ADC_CLK -min 0.0 [get_ports {RX_D[*]}] That creates a "virtual clock" that is sending the ADC data, and saying it is shifted by half a cycle. (I did not look at the LT data sheet, but think you described it that way). With this you should see a setup relationship of 4.781ns and hold relationship of -4.781ns. What that means is if the clock and data delays in the FPGA were perfectly aligned, you would meet setup/hold slack by 4.781ns. Another way to say it is they could skew from each other by +/-4.781ns and still meet timing. (Though the fitter should try to align them, though having a PLL in ssync mode will help) Next thing you need to do is account for the clock/data skew coming out of the ADC. Let's say it's +/-2ns, and let's say the board skews are 200ps. Then you would change the input -max value to +2.2ns and the -min value to -2.2ns. For DDR, there is a long document I wrote a long time ago, if you want to do some reading. Note that there are some templates you can just copy and paste from too: https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset01/source-synchronous-timing.pdf2.3KViews0likes0CommentsRe: How to count levels of logic in timing paths?
I'm guessing the last part, where the node locations increment by 3, e.g. N0, N3, N6, N9... are part of a carry-chain, which are not counted as a single logic level since they are much faster. I'm not sure how they're counted. But with the first part there are definitely distinct hops that should count as more than one. Personally, I've done timing closure on designs for ~20 years and have never found "levels of logic" that useful. There are just too many other things going on, such as carry-chain, fan-out, interconnectedness, etc. that it's not that useful. Plus, in the screen-shot above there is so much more info in the Data Path tab. You have a path with many levels, it crosses three LABs(Y112, Y111, Y109), and looks to be placed and routed really well. If you only had one failing path, maybe getting rid of a lab hop would help close timing, but most likely you have a number of paths, and many similar ones that just barely make timing, whereby squeezing this path down into fewer LABs will probably break another path. My first question would be why are the two endpoints in ALM registers? Do they have retiming restrictions that prevent Hyper-Retiming? When you run report_timing, click on the -extra_info all and it should give you info about retiming restrictions(plus other fun stuff).3.3KViews0likes0CommentsRe: About Metastability Summary for QuartusII Compilation Report
I wish the Metastability Report were used more, but people seem to want to ignore it. Note that if you go into Timing Analyzer and run Report Metastability(not just the summary), you can see all 206 chains analyzed to determine that number. It may be just a few synchronizers that are driving the final MTBF. Assuming you have Optimize for Metastability on(which is the default, and can be found under Assignments -> Settings -> Fitter), often the easiest way is to add another register to the chain(s).1.8KViews0likes0CommentsRe: Clock pessimism removal
Was able to see it with this, "report_timing -from [all_inputs] -setup -npaths 100 -pairs_only -extra_info none -detail full_path -panel_name {all input}" How come you have the incoming clock and data being generated from the clock sent out? I get that it is the topology, but basically you're asking for that delay to be completely removed by CCPP, so if you just describe the incoming clock and data with a create_clock, then it would work. My guess is what you're asking isn't feasible. CCPP removal doesn't just look for commonalities between Data Arrival and Required, but I believe is tied into the timing models. (Many years ago, when sending clock and data out for a source-synchronous transmit, we didn't fully remove all the CCPP between those paths, and it took a while for the timing analyzer to implement because it was pretty low-level. So I really doubt it will just work for your case. If I were to take a guess, the reason you want this is to synchronously timing the clock that is sent off chip and wrapped back around with the original clock that sends it?3.2KViews0likes0CommentsRe: We just installed 3 purchased copies of Quartus Prime on a lab network. The GUI opens and compiles properly but the "Messages" window does not show anything such as syntax errors, warnings, etc. Is it possible that our installer mis-set a default option?
There's a tab at the bottom of the Messages window, selecting between System and Processing messages. Is it possible you have the wrong one selected? I'v never heard of no messages showing. Also, at the top, there are options to filter the messages based on type or string matching. Maybe those are modified so nothing matches?713Views0likes0Comments