ContributorHow to constraint the min delay?
I use LCELLs to generate a pulse.
The verification engineer may use difference FPGA device to verify the design..
But the delay of LCELL in advance node FPGA is very small so that the pulse which is generated by LCELLs is very short.
And the design can't be changed.
So, I want to constraint the min delay between LCELLs.
I had tried following constraints. But it can't work.
Constraint:
set_min_delay 1.0 -from [get_pins lcell1|combout] \
-to [get_pins lcell2|data*]
set_net_delay -min 1.0 -from [get_pins lcell1|combout] \
-to [get_pins lcell2|data*]
How to constraint the min delay?
Thank you very much.
I haven't try to constrain a delay between combinational logic. Have you try to use the set_data_delay before?
I don't think the set_net_delay works with comb. logic but you can check the Ignored SDC Report and see whether the constraints have been applied in your design.
