NuvKFC
Contributor
ContributorHow to constraint the min delay?
I use LCELLs to generate a pulse.
The verification engineer may use difference FPGA device to verify the design..
But the delay of LCELL in advance node FPGA is very small so that the pulse whic...
I haven't try to constrain a delay between combinational logic. Have you try to use the set_data_delay before?
I don't think the set_net_delay works with comb. logic but you can check the Ignored SDC Report and see whether the constraints have been applied in your design.
