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NuvKFC's avatar
NuvKFC
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3 years ago
Solved

How to constraint the min delay?

I use LCELLs to generate a pulse. The verification engineer may use difference FPGA device to verify the design.. But the delay of LCELL in advance node FPGA is very small so that the pulse whic...
RichardT_altera's avatar
RichardT_altera
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3 years ago

There is a duplicate case with the same issue. Please refer to the case below (link attached) for further support.

https://community.intel.com/t5/Intel-Quartus-Prime-Software/How-to-constraint-min-delay-between-LCELLs/m-p/1383451#M73642


With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos and select the best solution.


  • NuvKFC's avatar
    NuvKFC
    Icon for Contributor rankContributor
    3 years ago

    Hi RichardTanSY_Intel

    Thank you, RichardTanSY_Intel, very much.

    Unfortunately, Quartus13.1 seem that don't support set_data_delay command.

    I will continuous follow the other one case.

    Thank you very much.