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Altera_Forum's avatar
Altera_Forum
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18 years ago

How to constraint clk signals output from PLL?

My system has two clock sources which are generated from PLL.

One is 80MHz for NiosII system

the other is 100MHz for custom IP which is integrated in NiosII system.

It seems that the two clocks corelate with each other automatically, so that I can't cut the timing analysis paths between these two clock domain.

So, I hope to tell the compiler that these two clock aren't corelated to each other and it isn't necessary to do timing analysis between them.

What can I do?

Thanks for any response...

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    With the Classic Timing Analyzer, use "Cut Timing Path" between the clock domains using the form of the PLL output node names you see in the timing report. If you have paths going in both directions between clock domains, add a cut-path setting for each direction.

    With TimeQuest, do something similar with set_false_path in each direction or use set_clock_groups.

    See the on-line help for these settings for more information.