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vlad's avatar
vlad
Icon for New Contributor rankNew Contributor
5 years ago

How to constrain the delays from ports to combinational block?

Hi! I'm trying to transmit data from one FPGA to another (DE1-SoC Cyclone V boards). The method I'm using is to have two wires, such that a transition on one wire means that a 0 is transmitted, and...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Vladislav,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY