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vlad's avatar
vlad
Icon for New Contributor rankNew Contributor
6 years ago

How to constrain the delays from ports to combinational block?

Hi! I'm trying to transmit data from one FPGA to another (DE1-SoC Cyclone V boards). The method I'm using is to have two wires, such that a transition on one wire means that a 0 is transmitted, and...
EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Vladislav

Thanks for your inquiry and sharing of your design constraint. Let me take a look and get back to you.

Thanks.

Eng Wei