New ContributorMy design has 2 gated clock from the same source CLK: 1. CLK_A is for modiule A, 2. CLK_B is for module B. The design needs to communication between module A and module B. How to constrain the clocks to meet the timing?
Regular ContributorDon't use gated clocks. Use the same global clock signal, and pass the enable signal into the modules and condition their operation with that enable. If you do this then all your circuits operate off the same clock signal, and the enable and data inputs just need to meet setup/hold with respect to the clock. You can then also employ the multicycle timing constraint to ease the implementation as well, possibly allowing for a higher clock rate. Gated clocks is generally a very bad idea as controlling skew between them because of the inline logic is hard.
Regular ContributorHi,
Refer below link & an433 which have similar example also recommendations are explained
page 10->https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/qts/qts_qii51006.pdf
Refer below link for Timing constrains
https://fpgawiki.intel.com/wiki/Timing_Constraints
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf
Regards
Anand
