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echen73
New Contributor
New ContributorHow to constrain clock
My design has 2 gated clock from the same source CLK: 1. CLK_A is for modiule A, 2. CLK_B is for module B. The design needs to communication between module A and module B. How to constrain the cl...
AnandRaj_S_Intel
Regular Contributor
Regular ContributorHi,
Refer below link & an433 which have similar example also recommendations are explained
page 10->https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/qts/qts_qii51006.pdf
Refer below link for Timing constrains
https://fpgawiki.intel.com/wiki/Timing_Constraints
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf
Regards
Anand
