How to constrain a parallel bus from a PLL clock?

Hi. I have a couple of questions about the my design. Basically I have an FPGA which has a big data table which the values are readed and sent to an external DAC. The reading process and the DAC are refreshed at 100 MHz. The 100 Mhz is generated internally by the ALTPLL.

1) Which is the correct way to constraint this design? I guess that set_multicycle_path constraint is required but I do not have clear the right way to do it. Some manuals advice that is better to generate virtual clock in order to constraint the design.

2) Also if the DAC data bus has different delays in the board, which is the way to make an internal delay in order to compensate the difference?

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