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Altera_Forum
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9 years ago

How to constrain a parallel bus from a PLL clock?

Hi. I have a couple of questions about the my design. Basically I have an FPGA which has a big data table which the values are readed and sent to an external DAC. The reading process and the DAC are ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi,

My main question is about how to calculate the right phase needed in the attached diagram. I guess the phase required is equal to the path delay involved in the ROM logic. Also I am wondering if the source - synchronous compensation mode in the ALTPLL can help to avoid these offset.