How to compress or reduce the binary size to the equivalent of an old FPGA

Hello,

In the binary file, there is a section that represents the device netlist, which is the customer logic implemented in the FPGA circuit. Therefore, the more complex the device, the more complex this section becomes. In other words, the configuration file for different devices are not comparable.

For a binary file, the compressed mode is already the smallest and FPGA-recognizable mode.

Best regards,

WZ