Forum Discussion
Abe
Frequent Contributor
7 years agoAdd the following to the vsim command ..
For Verilog designs:
-L altera_mf_ver -L altera_lnsim_ver -L 220model_ver -L altera_ver
For VHDL designs:
-L altera_mf -L altera_lnsim -L 220model -L altera