Honored Contributorhi, i have 3 vhdl file..its all my project file..how do i compile it and load it into the board because when i compile it showing top level entity undefined..im using quartus II 8.1..help me pleasee..
Honored ContributorYou need to write top level file, where you instantiate your project files.
Honored Contributorhow to write it, can you show me pleasee..?i'm really desperate right now coz i have to submit my project tomorrow...
Honored ContributorHere is nice example from Altera: http://www.altera.com/support/examples/vhdl/v_hier.html
Basically you need to connect your modules together in that vhdl top level file.Honored Contributorthanks...but i don't know to connect the module together..can you show me pleasee..
Honored ContributorI don't know what else you need, the link on Altera's website is the simplest way to explain how to regroup several components in a top level file.
Honored ContributorWe are here to help, not to do your homework assignments.
