Honored ContributorI have this VHDL code within my architecture:
architecture first of butterfly8 is signal butterfly8_r_Z1, butterfly8_r_Z2, butterfly8_r_Z3, butterfly8_r_Z4: std_logic_vector(31 downto 0); I know that I can use Vector Waveform File to monitor my waveform of INPUT and OUTPUT pins. Would it be possible to monitor my signal, such as butterfly8_r_Z1 in the architecture? If so, how to do it? Thanks
Honored Contributoruse virtual pins. goto Assignments => Assignment Editor, put Virtual Pin into the Assignment Name column, change the value to On, make sure Enabled is set to Yes, and select the nodes to apply this to. You can use wildcards in the To column.
Honored ContributorI have assigned all my input and output pins of FFT to VIRTUAL PINS. However, when I compiled it, it still telling me I have insufficient pins. Anyone know why?
Honored ContributorHonored ContributorThx, KAZ. Do you mean I need something like parallel to serial converter (to convert the 128 input points from P to S). Then, wait (store in memory) until 128 points available and start the FFT process. Is this going to be a problem with the latency or delay?
Honored ContributorI don't see why you need to do par/ser conversion. I can assume your input isn't that wide e.g. it could be ADC output with finite bitwidth.
If you are using altera fft then it will do the job of waiting for you. So all you have to do is to input to your fft the correct set of inputs then read the output. Normally fft will output one block late(receive time + processing time), this shouldn't matter. I don't know of any fft that can output straightaway because it needs to have all points ready first. each ouput point is eventually computed from the scaled sum of products of all input points. Since you are a beginner I don't see why you use floating point. You better use fixed point(2's complement) and 16 bit real/imag is adequate for the most demanding applications.Honored ContributorI am actually writing my own FFT module in which is 128-points FFT size. I am using floating-point as I have found the library in Quartus II. Are there any libraries for fixed-point implementation?
By the way, what if I have a VHDL design that I want to use as a component. And this VHDL design has many I/O ports as well. What is the best way to perform compilation and simulation? Is it using Virtual Pins as mentioned by thepancake?Honored Contributoruse numeric_std library.
use singed type in your vhdl code (and use std_logic at io), you can easily cast or convert between these two types. Do your internal computation all in signed. use 16 bit real and 16 bit imag. In your case you must have adequate storage for your fft points per computation. I don't know details of the fast fourier computation technology but I know it splits up the full set of points into smaller sets, unlike traditional DFT which used to deal with the whole vector. You will need loads of multipliers and adders in all cases. Therefore, you don't need to think of virtual pins. I wouldn't care about it for now. It is used occasionally as explained by the pancake.Honored ContributorThanks. Yes, I splits the FFT up into smaller sets (the butterfly computation). And each of these smaller sets, I write a VHDL code and treat it as a component and call it in my high-level design. What if I am writing a low-level VHDL code (which I will use it as a component of my FFT) and it has many I/P ports, and I would like to perform a small simulation? Should I also use the way you mentioned?
One more last question: If say I am using 128-point FFT. Is it the 128 real and imaginary inputs will take turn to input to the device using 16 bits real and 16 bits imag input pins?Honored ContributorFor simulation, yes use virtual pins to tell quartus not to bother about them or you can use other logic tricks to remove some of your io.
The 128 pairs will come in successively. real and imaginary are better fed in parallel(not interleaved).Honored ContributorThank you so much all! Since I just want to perform simulation (for smaller sets), I will use the virtual pins to perform simulation.
However, for the high-level, I will use the method suggested by KAZ where only 16-bit for real and 16-bit for imag are use. And the 128 inputs take turns to input to the device. But, why even I have assigned all the I/O pins as virtual pins, the message of 'can't place pins due to device constraints' still pop up? Any suggestions? I have checked with the Pin Planner and all the I/O pins gone. So, I am quite sure I have assigned the virtual pins properly.
