How to bypass setup and hold time checks in Altera-Modelsim

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Hi there,

I am designing a special measuring circuit in which setup and hold times of FF are sometimes violated. When they happen, the related signals become undefined 'X', thus compromising the rest of the gate simulation in Modelsim (Cyclone II models, from Quartus II).

How is it possible to disable setup and hold time checks during simulation?

I reviewed the code in the Cyclone II (Vital) models, and there is indeed a flag CheckInfo.Violation. Depending on this flag, the check is or isn't performed. How to set that flag to a desired value?

Finally, in Quartus II, (Settings -> EDA Tool Settings -> Simulation -> More EDA Netlist Writer Settings), there is an option called "Disable detection of setup and hold time violation in the input resisters of bi-directional pins". I turned in On, but it does not have any effect in the simulation. I think this option is clearly not applicable to registers in logic elements.

Thanks in advance!

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Hi,

I'm not sure that this will work with an external Simulator, but you can try the setting

"Show 'X' on timing violation" in the Asignment editor. Look into the attachment.

Kind regards

GPK

Hello GPK, great idea, thanks a lot.

However, I tried different setting combinations of 'Show X on timing violations' and 'Setup and hold time violation', but none has worked in the Modelsim run.

Does anyone know how to disable this check directly in the Modelsim environment?

Thank you.

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Hello GPK, great idea, thanks a lot.

However, I tried different setting combinations of 'Show X on timing violations' and 'Setup and hold time violation', but none has worked in the Modelsim run.

Does anyone know how to disable this check directly in the Modelsim environment?

Thank you.

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Hi,

as far as I know there is a verilog command line option called "+notimingchecks".

Maybe you can look in the modelsim help :rolleyes:

Kind regards

GPK

GPK,

Brilliant! If I pass the parameter +notimingchecks in the vsim command line, the timing checks are disabled.

Nice work, Thank you very much.

C.

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GPK,

Brilliant! If I pass the parameter +notimingchecks in the vsim command line, the timing checks are disabled.

Nice work, Thank you very much.

C.

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;);) maaaan you are a walking joke ;). why the hell are you simulating in a timing simulation model if you didnt need timing delay information. by this command you basically disabled all the timing analysis and now it became a functional simulation. if you are ok with just functional simulation, compile your project's verilog file itself. and simulate it. without using .sdf(sdo) and without .vo files and it won't simulate any timing,it will be just a functional simulation and you will not have to enter this +notimingchecks command at all. (by the way if you enter into simulation optimization options there is a checkbox for that, named "disable timing checks (+notimingchecks)" . check it and start the simulation.)

does anyone know how to disable Red X -es With the timing simulation? (without using +notimingchecks). allright i get it, there is a violation but i do not care. i want to see my signal.