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Altera_Forum
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16 years ago

How to bypass setup and hold time checks in Altera-Modelsim

Hi there, I am designing a special measuring circuit in which setup and hold times of FF are sometimes violated. When they happen, the related signals become undefined 'X', thus compromising th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Hello GPK, great idea, thanks a lot.

However, I tried different setting combinations of 'Show X on timing violations' and 'Setup and hold time violation', but none has worked in the Modelsim run.

Does anyone know how to disable this check directly in the Modelsim environment?

Thank you.

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Hi,

as far as I know there is a verilog command line option called "+notimingchecks".

Maybe you can look in the modelsim help :rolleyes:

Kind regards

GPK