Forum Discussion
RNeto2
New Contributor
6 years agoThank you all for the replies, I am indeed a beginner in FPGAs and Verilog, so I appreciated all the input and the opportunity to read up more on the subject. A bit more reading drove me straight to the solution and I ended up fixing it as such:
A simple syntax issue, now the buses from my schematic fully align with my pins and I ran the code successfully. I will probably end up taking the free training courses to avoid more simple issues like this.
Also, I am using both schematic and HDL solely due to the visual aspect and the low complexity of the project ( it's just a low pass filter ).
Ricardo