Forum Discussion
vj123
New Contributor
6 years agoAs per my understanding you are facing issue while instantiating the Ord5_FIR_direct module & that too during compilation itself.
what errors you are getting while compilation? if possible share here HDL file in code snippet
you can try like below temporary wires duing instantiation at place of bMKR_A & bMKR_D & assign these wires to ports pin ENTRADA & SAIDA respectively in your top module & this is my guess since we don`t have clear picture of top module.
wire [7:0] temp_A;
wire [11:0] temp_D;