How to assign each bus bit from a schematic to board pin?

@RNeto2​ , unless I'm completely misunderstanding you, it sounds like you are trying to access the FPGA IO pins via a Verilog program. But nothing you've provided allows you to do that. The top level HDL program will not have a port map as in the code you've provided. Instead, you tell it the pins in a constraint file (or via pin planner as @sstrell​ ). But your "schematic" does not list the FPGA pins. You need to trace it back to where it connects to the FPGA.

I'm assuming you are new to FPGA's ? It's too much to explain in a forum post. Altera has some outstanding free training found here:

https://www.intel.com/content/www/us/en/programmable/support/training/catalog.html

The "Become an FPGA Designer in 4 hours" is great as are most of the others.