how to apply timing constrain for this code

hi forum,

i just want to know how to properply apply constrains in timequest for this , and i want to false path and cirtical path or multicycle path in the following design. thanks a lot

regards,

baba

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

ENTITY xxyy IS

PORT( clock : IN STD_LOGIC;

ho_total : IN std_logic_vector(11 downto 0);

h_forpch : IN std_logic_vector(7 downto 0);

h_swd : IN std_logic_vector(8 downto 0);

ve_total : IN std_logic_vector(11 downto 0);

v_forpch : IN std_logic_vector(3 downto 0);

v_swd : IN std_logic_vector(3 downto 0);

ho_on : IN std_logic_vector(9 downto 0);

ve_on : IN std_logic_vector(5 downto 0);

DE_out : OUT STD_LOGIC;

hs_out : OUT STD_LOGIC;

vs_out : OUT STD_LOGIC);

END xxyy ;

ARCHITECTURE rtl OF xxyy IS

SIGNAL hs, vs,v_on_h,v_on_v : STD_LOGIC := '1';

SIGNAL h_count,v_count : STD_LOGIC_VECTOR( 11 DOWNTO 0 ) := (others=>'0');

begin

PROCESS(clock,ho_total,h_forpch,h_swd)

BEGIN

if rising_edge(clock)

IF ( h_count = ho_total) THEN -- horizontal counter

h_count <= (others=>'0');

ELSE

h_count <= h_count + '1';

END IF;

IF (h_count <= h_swd and h_count >= h_forpch) THEN -- h sync generation

hs <= '1';

ELSE hs <= '0';

END IF;

IF (h_count >= ho_on) THEN -- video on horizontal for active displaygeneration

v_on_h <= '1';

ELSE

v_on_h <= '0';

END IF;

IF (v_count >= ve_on) THEN -- video on vertical for active displaygeneration

v_on_v <= '1';

ELSE v_on_v <= '0';

END IF;

end if;

end process;

PROCESS(hs,ve_total,v_forpch,v_swd,h_count,v_count)

BEGIN

if rising_edge(hs) -- vertical counter

v_count <= v_count + '1';

end if;

IF (v_count = ve_total) THEN -- vertical counter clear

v_count <= (others=>'0');

end if;

IF (v_count <= v_swd and v_count >= v_forpch) THEN -- v sync generation

vs <= '1';

ELSE

vs <= '0';

END IF;

end process;

hs_out <= hs;

vs_out <= vs;

DE_out <= v_on_h AND v_on_v;

end rtl;