how to apply timing constrain for this code

You need to clean up your VHDL before you work on the timing constraints. Besides a couple of syntax errors for missing "then"s, you have some problems with your process statements. The sensitivity lists for registered logic should contain only the clock and asynchronous control signals like reset. The second process statement should be changed to separate process statements for registered logic and for combinational logic. See http://www.alteraforum.com/forum/showthread.php?t=1025 for coding style references in the Quartus handbook and elsewhere.

After you have changed to a standard coding style, consider changing the hs ripple clock to a clock enable. See http://www.alteraforum.com/forum/showthread.php?t=2388 for more information about this. If the hs clock changed to a clock enable is doing a divide-by-n function, then you can use a multicycle setup of n and multicycle hold of n-1. I can't tell whether hs can be reduced to a simple divide by n that can use a clock enable.