how to apply timing constrain for this code

I take it you know how to make clock constraints and I/O constraints, and are just looking for multicycles and false paths? To be honest, that's a function of the design, and nobody knows this design as well as you do. If you want to be more specific and describe how a specific path behaves and if it's a multicycle or false path, that might make more sense.

(Just quickly, false paths are generally between asynchronous clocks, so there's no way to determine what the requirement should be since the clocks are constantly changing their relationship. These are easy to constrain with a false_path, but difficult to design for since all sorts of other things need to be taken into account(metastability, different delays to differnet destinations, etc.) Multicycles generally means the data transfers through the registers at a lower rate. For example, if the source and destination clocks are both 10ns, but the data only goes through on every other clock cycle, than you can multicycle those paths. That's just a really quick description, as there are plenty of other cases.