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Altera_Forum
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10 years ago

How do I split a bus into individual signal lines?

I have a schematic that is supposed to take a 4 bit bus and then split off the individual lines into TTL logic. I created a 4 bit bus pin "in[3..0]" then connected a bus line. Then connected individual node lines from that to the TTL logic. The problem is that it wont let me specify which individual node line I want. I tried right clicking the node line and then properties, but there is nothing useful there. It would probably work if there was a way to give the individual node line a name like "in[0]" or similar.

I found a help file that said to highlight the node line and then go to the edit menu and click "Line Properties" but no such thing exists. There is a "properties" but it is deactivated. Another help file said this:

--- Quote Start ---

You open this dialog box by right-clicking a node in the all pins or groups list and then clicking node properties.

Allows you to view the node name and view or change the assignments for the selected node. You can assign a specific pin to the node, create an I/O standard assignment, and reserve the pin for future use. You can also view specific location and function information about the pin.

--- Quote End ---

But there is no "All pins" button anywhere that I can find.

Does anybody know how to make buses work properly in Quartus v15? I searched and found nothing useful.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    I haven't had time to play with it, but I noticed that the software has a "convert schematic to HDL file" option. It should be interesting to see what code it generates.

    I found this code example of an HDL ripple counter: 

    module counter( clk, count );
input clk;
output count;
reg count;
wire clk;
initial
    count = 4'b0;
always @( negedge clk )
    count <= ~count;
always @( negedge count )
    count <= ~count;
always @( negedge count )
    count <= ~count;
always @( negedge count )
    count <= ~count;
endmodule

    It is certainly more complicated from the source code point of view, but I am going to have to experiment to see which version uses fewer LE's. It looks like a series of one bit synchronous counters which is what a ripple counter is. There are no "+" signs.

    The thing about ripple counters and FPGA's is just what you said, however, if your logic doesn't care about the parallel output, then a ripple counter is fine. In my clock dividers, the only thing I care about is that the output of a particular pin is a stable frequency. Ripple counters are fine for that since I'm not interested in the counter output as a whole and propagation delay is mostly irrelevant in that case. When I actually start work on the VGA controller, the timing is far more critical and synchronous counters are the only things that will work.

    Right now I'm working on an RS-232 asynchronous serial port. I know I'm just reinventing the wheel, but its how I learn.