How do I split a bus into individual signal lines?

I haven't had time to play with it, but I noticed that the software has a "convert schematic to HDL file" option. It should be interesting to see what code it generates.

I found this code example of an HDL ripple counter:

module counter( clk, count );
input clk;
output count;
reg count;
wire clk;
initial
    count = 4'b0;
always @( negedge clk )
    count <= ~count;
always @( negedge count )
    count <= ~count;
always @( negedge count )
    count <= ~count;
always @( negedge count )
    count <= ~count;
endmodule

It is certainly more complicated from the source code point of view, but I am going to have to experiment to see which version uses fewer LE's. It looks like a series of one bit synchronous counters which is what a ripple counter is. There are no "+" signs.

The thing about ripple counters and FPGA's is just what you said, however, if your logic doesn't care about the parallel output, then a ripple counter is fine. In my clock dividers, the only thing I care about is that the output of a particular pin is a stable frequency. Ripple counters are fine for that since I'm not interested in the counter output as a whole and propagation delay is mostly irrelevant in that case. When I actually start work on the VGA controller, the timing is far more critical and synchronous counters are the only things that will work.

Right now I'm working on an RS-232 asynchronous serial port. I know I'm just reinventing the wheel, but its how I learn.