How do I choose between more than two values in verilog

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I'm working on a project that requires me to improve on an already existing project. The contains this syntax

wire [15:0]music1=(instru)?music1_ramp:music1_sin;

which is to choose between music1_ramp and music1_sin. I want to expand this in such a way that I can choose between more than two options (say five), please can anyone tell me a syntax I could use to do this as I am still new to the language

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assign music1 = (instru1) ? music1_ramp:

(instru2) ? music2_ramp:

(instru3) ? music3_ramp:

music5_sin; //default

You can also change the logic to use an always block if the conditional syntax gets unruly:

reg  music1;
always @* begin
    if(instru1)         music1  = music1_ramp;
    else if(instru2)    music1  = music2_ramp;
    else if(instru3)    music1  = music3_ramp;
    else if(instru4)    music1  = music4_ramp;
    else                music1  = music5_ramp;
end

This should produce the same logic as the conditional but may be easier to read for some.

Jake