How declare ALM synchronous signal (enable, sload, sclear) in vhdl

You can access a complete template for all secondary control signals using the Edit menu in the Quartus text editor. But here is a similar complete template. Just remove the signals you don't want to use:

ARCHITECTURE behavior OF dff IS
BEGIN
PROCESS(clk, aclr, apre, aload, adata)
BEGIN
    IF aclr = '1' THEN
        q <= '0';
    ELSIF apre = '1' THEN
        q <= '1';
    ELSIF aload = '1' THEN
        q <= adata;
    ELSIF rising_edge(clk) THEN
        IF ena = '1' THEN
            IF sclr = '1' THEN
                q <= '0';
            ELSIF sload = '1' THEN
                q <= sdata;
            ELSE
                q <= d;
            END IF;
        END IF;
    END IF;
END PROCESS;
END ARCHITECTURE behavior;