New ContributorHow can i turn off the optimization completely, I suspect that optimization is doing something with the output.
I am using Quartus Prime Lite as software and MAX V CPLD as the device
Super ContributorWhat optimization are you referring to? What is the issue? Posting some code and more details about the exact issue would help.
#iwork4intel
New Contributorlibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Control is
Port (
-- INPUT INTERFACES
CLK : in std_logic; -- system clock Input
PS1_Fail : in std_logic; -- PS1 Fail
PS2_Fail : in std_logic; -- PS2 Fail
Reset : in std_logic; -- Reset
-- OUTPUT INTERFACES
PS_Fail_Detect : buffer std_logic :='1'; -- Gates PS Fail Detect Output
);
end Control;
architecture Behavior of Control is
SIGNAL PS_Trigger : std_logic := '0'; -- OR Gated fault Output
begin
HANDLE_CONTROL : process (CLK)
begin
if(rising_edge(CLK)) then
PS_Trigger <= (PS1_Fail or PS2_Fail); --PS1_Fail & PS1_Fail are grounded for verification
end if;
end process;
TRIGGER_PSFAULT : process(CLK)
TYPE StateMachine IS(LatchFault,WaitForReset); --state machine data type
VARIABLE FDState : StateMachine := LatchFault; --State machine variable
begin
if(rising_edge(CLK)) then
if(Reset = '1') then
case(FDState) is
when LatchFault =>
if (PS_Trigger = '1') then -- how can this line return true if PS1_Fail and PS2_Fail are low
PS_Fail_Detect <= '0'; -- on startup this signal becomes low, once I give a reset everything works good
FDState := WaitForReset;
else
PS_Fail_Detect <= '1';
end if;
when others =>
null;
end case;
elsif(Reset = '0') then
PS_Fail_Detect <= '1';
FDState := LatchFault;
end if;
end if;
end process;
end Behavior;
New ContributorPS_Fail_Detect becomes low, even though PS1_Fail and PS2_Fail are low
Regular ContributorHi,
Have you verified the design using the testbench?
what you observed for different combinations of PS1_Fail and PS2_Fail?
Regards,
Vicky
Regular ContributorHi,
May I know any update?
Should I considered as case to be closed?
Regards,
Vicky
New ContributorHi, Vicky I tested the logic using testbench and the resutls were satisfactory, in case of CPLD the result in different, I am facing another issue in using the same CPLD, and I belive that it may be due to the optimizations enabled in quartus by default, I tried turning off the "VHDL state machine extraction" feature but got no success.
If the line "testled <= NOT testled" is commented then the behavior of RTL becomes change I have observed a change in the net-list as well.
CONFIGURE_ADC : process(clk) is
variable fifo_memory : fifo_memory_type := (X"04",X"13");--(X"08",X"7B");
variable read_memory : read_data_type := (X"00", X"00", X"00", X"00");
variable fifo_head : integer range 0 to 1 := 0;
variable read_head : integer range 0 to 3 := 0;
variable counter : integer range 0 to 65535 := 0;
begin
if rising_edge(clk) then
if(microseconds > 3000000) then
case confstate is
when X"0" =>
fifo_head := 0;
cs_n <= '0';
testled <= NOT testled; -- if this line is commented or removed the code starts misbehaving and state machine does not propagate in the required manner
if(busy_transfer = '0') then
read_head := 0;
read_memory(read_head) := spi_rx_data;
spi_tx_data <= fifo_memory(fifo_head);
confstate <= confstate + 1;
else
confstate <= X"0";
end if;
when X"1" =>
trigger_transf <= '1';
confstate <= confstate + 1;
fifo_head := 1;
when X"2" =>
if(busy_transfer = '1') then
trigger_transf <= '0';
confstate <= confstate + 1;
end if;
Super ContributorIf you are trying to build a state machine with this code, this is not the way to do it. confstate should be set as an enumerated data type with specific states. You should also have separate processes for the next state logic (a clocked process) and what the outputs should be in each state (logic process). I don't see why testled is causing a difference in behavior because you don't show how testled is defined.
Again, in most cases, optimization settings do not affect the functionality of a design. It's better to focus on debugging the actual code before thinking an optimization setting is at fault.
#iwork4intel
New Contributorsstrll, this was just a quick test code, I have already tried it with enumerated data type with specific states as you mentioned but the result is still same, the behaviour was worse when "EXTRACT VHDL STATE MACHINE" optimization was enabled, however after turning that off things got better but this issue still persists.
TestLed is a standard logic output mapped to a pin on CPLD.
New ContributorMoreover for your information the code works fine in simulation
Regular ContributorHi,
For Optimization settings navigate to below,
Assignments -> Settings->Compiler Settings...(Advanced Settings)
Regards,
Vicky
