How can i turn off the optimization completely

Hi, Vicky I tested the logic using testbench and the resutls were satisfactory, in case of CPLD the result in different, I am facing another issue in using the same CPLD, and I belive that it may be due to the optimizations enabled in quartus by default, I tried turning off the "VHDL state machine extraction" feature but got no success.

If the line "testled <= NOT testled" is commented then the behavior of RTL becomes change I have observed a change in the net-list as well.

CONFIGURE_ADC : process(clk) is

variable fifo_memory : fifo_memory_type := (X"04",X"13");--(X"08",X"7B");

variable read_memory : read_data_type := (X"00", X"00", X"00", X"00");

variable fifo_head : integer range 0 to 1 := 0;

variable read_head : integer range 0 to 3 := 0;

variable counter : integer range 0 to 65535 := 0;

begin

if rising_edge(clk) then

if(microseconds > 3000000) then

case confstate is

when X"0" =>

fifo_head := 0;

cs_n <= '0';

testled <= NOT testled; -- if this line is commented or removed the code starts misbehaving and state machine does not propagate in the required manner

if(busy_transfer = '0') then

read_head := 0;

read_memory(read_head) := spi_rx_data;

spi_tx_data <= fifo_memory(fifo_head);

confstate <= confstate + 1;

else

confstate <= X"0";

end if;

when X"1" =>

trigger_transf <= '1';

confstate <= confstate + 1;

fifo_head := 1;

when X"2" =>

if(busy_transfer = '1') then

trigger_transf <= '0';

confstate <= confstate + 1;

end if;