How can i turn off the optimization completely

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity Control is

Port (

-- INPUT INTERFACES

CLK : in std_logic; -- system clock Input

PS1_Fail : in std_logic; -- PS1 Fail

PS2_Fail : in std_logic; -- PS2 Fail

Reset : in std_logic; -- Reset

-- OUTPUT INTERFACES

PS_Fail_Detect : buffer std_logic :='1'; -- Gates PS Fail Detect Output

);

end Control;

architecture Behavior of Control is

SIGNAL PS_Trigger : std_logic := '0'; -- OR Gated fault Output

begin

HANDLE_CONTROL : process (CLK)

begin

if(rising_edge(CLK)) then

PS_Trigger <= (PS1_Fail or PS2_Fail); --PS1_Fail & PS1_Fail are grounded for verification

end if;

end process;

TRIGGER_PSFAULT : process(CLK)

TYPE StateMachine IS(LatchFault,WaitForReset); --state machine data type

VARIABLE FDState : StateMachine := LatchFault; --State machine variable

begin

if(rising_edge(CLK)) then

if(Reset = '1') then

case(FDState) is

when LatchFault =>

if (PS_Trigger = '1') then -- how can this line return true if PS1_Fail and PS2_Fail are low

PS_Fail_Detect <= '0'; -- on startup this signal becomes low, once I give a reset everything works good

FDState := WaitForReset;

else

PS_Fail_Detect <= '1';

end if;

when others =>

null;

end case;

elsif(Reset = '0') then

PS_Fail_Detect <= '1';

FDState := LatchFault;

end if;

end if;

end process;

end Behavior;