How can I simulate verilog and vhdl in one project with ModelSim-Altera?

I think ModelSim-Altera doesn't support mixed language simulation.

you can check it here :

http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html

you need to write you testbench in same language with your IP.

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I think ModelSim-Altera doesn't support mixed language simulation.

you can check it here :

http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html

you need to write you testbench in same language with your IP.

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Thanks for the reply.

ModelSim-Altera doesn't support mixed language simulation, but ModelSim SE support. What should I do?

If you can afford a fund, you should buy ModelSim SE/PE in order to perform mixed language simulation, but if you can't then you have to write your testbench in same language with your IP like I said before, or you can find another IP written in same language with your testbench,..

I hope it can help you,...

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If you can afford a fund, you should buy ModelSim SE/PE in order to perform mixed language simulation, but if you can't then you have to write your testbench in same language with your IP like I said before, or you can find another IP written in same language with your testbench,..

I hope it can help you,...

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Thanks.

I have made it in ModelSim SE.