Forum Discussion

Honored Contributor

15 years ago

How can I simulate verilog and vhdl in one project with ModelSim-Altera?

I have a IP in vhdl, and I writed a testbench in verilog to test the IP. How can I simulate the project in ModelSim-Altera? Thanks.

Honored Contributor

15 years ago

--- Quote Start ---

I think ModelSim-Altera doesn't support mixed language simulation.

you can check it here :

you need to write you testbench in same language with your IP.

--- Quote End ---

Thanks for the reply.

ModelSim-Altera doesn't support mixed language simulation, but ModelSim SE support. What should I do?