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Altera_Forum's avatar
Altera_Forum
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15 years ago

How can I simulate verilog and vhdl in one project with ModelSim-Altera?

I have a IP in vhdl, and I writed a testbench in verilog to test the IP. How can I simulate the project in ModelSim-Altera? Thanks.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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If you can afford a fund, you should buy ModelSim SE/PE in order to perform mixed language simulation, but if you can't then you have to write your testbench in same language with your IP like I said before, or you can find another IP written in same language with your testbench,..

I hope it can help you,...

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Thanks.

I have made it in ModelSim SE.