How can i save a constant value on a FPGA for a comparison?

Hello,

i'm searching for a easy way to save a constant value (std_logic_vector) on a FPGA. For example, i need to save something like that: 101000101010010, because i want to compare two bitstrings. At frist i create such a Bitstring on the FPGA with some ring oscillators and then i save it on the FPGA with copy and paste. After this i want to create a new one to compare it with the first one. After this the FPGA shows the difference. The creation (http://www.dict.cc/englisch-deutsch/creation.html) and the comparison is done by a controller.

I tried it like this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity verification_reg is
    
    generic (
      bit_length    : integer := 3160
    );
    
    port (
    -- Output port    
      verification_responses_out                : out std_logic_vector((bit_length - 1) downto 0)
    );
end verification_reg;
architecture arch of verification_reg is
    
   begin
      verification_responses_out <= "00000000000000000000000..........00111111"
end arch;

It works, but i have a Problem. I create and save such a Bitstring, but this saved bitstring confuses the ring oscillators on the FPGA. The difference between the "old" and "new" bitstring is very high. If i don't change the saved bitstring the difference is very small. Is it possible to save a bitstring on the FPGA, without to confuse the FPGA?

Thank you for the help and sorry for my very bad english. :)

Mime