How can i save a constant value on a FPGA for a comparison?

Logic lock regions are going to be no good - it will still spread the logic around differently on each compilation. You will need to manually place and route each lut and register yourself to get a consistant result.

I dont know how to make a pre-compiled netlist, I have never done it - Ill let someone else answer,.

But your ring oscillators are going to affected by PVT - process voltage temerature. Their frequency and duty cycle will change according to these uncontrollable factors.

The last sentence is due to auto text from my phone. I meant to say - why do you have ring oscilators? they are far to prone to PVT and P&R changes. Why not just use a PLL?