Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

How can i save a constant value on a FPGA for a comparison?

Hello, i'm searching for a easy way to save a constant value (std_logic_vector) on a FPGA. For example, i need to save something like that: 101000101010010, because i want to compare two bitst...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi!

Yes, the ROs are made using logic.

I forgot to say, that i tried it with "logic lock regions" without a better result. Still a very high difference. What do you mean with lock the ring oscillators?

And could you explain shortly how i can pre compile the ROs into a post p&r netlist.

I don't understand your last sentence, why should i "hate" this? :D

Sorry my english is very bad :D