Altera_Forum
Honored Contributor
Honored ContributorHow can I generate time limited sof file?
Hi,
My design is not uses cores without licence, but I need to generate "time limited" file to demonstrate. Can I do it?Forum Discussion
6 Replies
Altera_Forum--- Quote Start --- Hi, My design is not uses cores without licence, but I need to generate "time limited" file to demonstrate. Can I do it? --- Quote End --- I will set a counter and at the end disable the logic.- Altera_Forum
Thanks, kaz, I understand it. But I don't want made any changes in my code, I just want generate another file. Is it possible?
- Altera_Forum--- Quote Start --- Thanks, kaz, I understand it. But I don't want made any changes in my code, I just want generate another file. Is it possible? --- Quote End --- I doubt it is possible as altera doesn't provide such option for field use. You may drive the configuration pins to clear the fpga from outside fpga or inside(using counter idea)
- Altera_Forum
Doesn't a design run for like an hour if you have an IP that requires a license? I'm not sure but if that's the case. Could you just add the IP without "using" it?
- Altera_Forum
Thanks kaz, Rodo!
I think the simplest way for me is use some IP Core in evaluation mode without using it... I'll try it tomorrow, thanks - Altera_Forum
The Altera time limited files contain additional logic. I'd use the counter as described above.
