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fengtianwenming's avatar
fengtianwenming
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2 years ago

How can I convert a Verilog code file into a BDF file

I'm currently using Quartus 18.0. I've successfully written Verilog files that compile and simulate without any issues. However, I'm now seeking to generate BDF files directly from these Verilog code...
Hdl
fengtianwenming's avatar
fengtianwenming
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2 years ago

Thank you for your response. It seems you've correctly interpreted that "Create symbol file for current file" might be used to generate a symbol file (BSF file) for the code file, enabling its integration into a schematic. However, the challenge I'm facing is that I'm seeking to convert Verilog code into a BDF file containing the internal gate-level circuitry. I want to manipulate and modify it directly, akin to the detailed circuits visible in the RTL Viewer. Do you have any suggestions or methods to accomplish this?

sstrell's avatar
sstrell
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2 years ago
No there’s no way to do that. In the long run, learning an HDL is going to be way more beneficial and time-saving vs manipulating a schematic.
  • fengtianwenming's avatar
    fengtianwenming
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    2 years ago

    Thank you for your response. I'm sad to hear about this fact.