How are timing assignments set?

What you're seeing is the combinatory propagation delay from "b" to "c", through the logic that implements it.

There's no way to make it instantaneous; but sometimes, it can be made faster.

You can try to set the synthesis and fitter options set to "speed", instead of area or balanced.

You can also try to use a more modern version of Quartus and use TimeQuestl, instead of the Classic Timing Analyzer.

And of course, you can try to figure out why the combinatory path is so long and see if there's a shorter way.

How I imagine the synthesizer would implement this is with a multiplexer. Therefore, the combinational logic should be very simple. So, I don't understand why it takes so long to settle. I can't think of any other logic that would be faster.

What's stranger to me, however, is the amount of time it takes for c to even begin to change from dn to dn+1. It's about 10 ns which means that the signal b must be taking a route of about 3 metres. 3 metres in a chip that is about a square inch in size! Unless for some reason the signal does not travel at the speed of light.

This last problem could be solved by somehow forcing the fitter to choose a shorter route. I had guessed that this is what timing assignments did. But are you saying that timing assignments cannot be used to solve my problem? Your sole suggestion seems like something that would simply tell the fitter to make all routes shorter rather than singling out a single problematic path.

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How I imagine the synthesizer would implement this is with a multiplexer. Therefore, the combinational logic should be very simple. So, I don't understand why it takes so long to settle. I can't think of any other logic that would be faster.

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This is what I'd say as well. Are b, and d* registers?

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What's stranger to me, however, is the amount of time it takes for c to even begin to change from dn to dn+1. It's about 10 ns which means that the signal b must be taking a route of about 3 metres. 3 metres in a chip that is about a square inch in size! Unless for some reason the signal does not travel at the speed of light.

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The electrical field travels at speed of light. Though the speed of light in sillicon dioxide is slower than in vacuum. But that's a minor issue.

The big issue is that the transistors take time to change state. That is the main contributor to the propagation delay.

Since you're using a very old Quartus, I assume you're also dealing with a very old FPGA/CPLD. A 10 ns delay even for such simple logic does not look too surprising.

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This last problem could be solved by somehow forcing the fitter to choose a shorter route. I had guessed that this is what timing assignments did. But are you saying that timing assignments cannot be used to solve my problem? Your sole suggestion seems like something that would simply tell the fitter to make all routes shorter rather than singling out a single problematic path.

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Your thinking is correct.

Quartus does have timing driven synthesis and fitting: you specify timing constraints and the software tries to optimize the design as much as needed until your constraints are met.

And this is the default approach nowadays.

But with such an old version as 5.0.. IIRC it doesn't work so well.

That's why I suggested a more modern Quartus and TimeQuest.

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Are b, and d* registers?

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b is a register. d is not.

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Quartus does have timing driven synthesis and fitting: you specify timing constraints and the software tries to optimize the design as much as needed until your constraints are met.

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So, how would I specify a timing constraint that would force c to change to d within, let's say, 5 ns of b changing?